1. Field of the Invention
The present invention relates to a clock synchronous semiconductor memory device, and more particularly, to a semiconductor memory device which implements a DLL (Delay Locked Loop) circuit for synchronizing an internal clock signal used in internal circuitry to an external clock signal.
2. Description of the Related Art
Recently, such semiconductor memory devices as an SDRAM (Synchronous DRAM) implement a DLL (Delay Locked Loop) circuit for synchronization of output timing of read data with an external clock signal. By using the DLL circuit, the phase of a controlling clock signal for controlling a data output circuit is adjusted to the phase of the external clock signal so that read data is output in synchronization with the external clock signal. The basic configuration of the DLL circuit has been disclosed, for example, in Japanese Unexamined Patent Application Publication No. Hei 10-11 2182.
FIG. 1 shows the operation of an SDRAM having a DLL circuit. The SDRAM receives an external clock signal CLK with its clock buffer, and generates an internal clock signal ICLK (FIG. 1(a)). The internal clock signal ICLK lags behind the external clock signal CLK by a delay time tD of the clock buffer. The delay time tD is a fixed time independent of the frequency of the external clock signal CLK. The SDRAM also generates an adjusted clock signal DLLCLK having the same phase as that of the external clock signal CLK, by using the internal clock signal ICLK (FIG. 1(b)).
In this example, the SDRAM receives a read command R1 in association with the zeroth external clock signal CLK and receives a write command W1 in association with the first external clock signal CLK.
A data output circuit outputs read data Q1 corresponding to the read command R1 to a data terminal DQ in synchronization with the rising edge of the adjusted clock signal DLLCLK that corresponds to the second external clock signal CLK (FIG. 1(c)). That is, the read data Q1 is output as lagging behind the rising edge of the second external clock signal by a delay time tDAC of the data output circuit (read latenc=2). Consequently, the access time tAC with respect to the external clock signal CLK is equal to the delay time tDAC. The system on which the SDRAM is mounted receives the read data Q1 in synchronization with the rising edge of the third external clock signal CLK.
Meanwhile, write data D1 corresponding to the write command W1 is supplied in time with the rising edge of the first external clock signal CLK, along with the write command W1 (FIG. 1(d)). This operation is referred to as an operation of write latency xe2x80x9c0xe2x80x9d. A data input circuit receives the write data D1 in synchronization with the rising edge of the internal clock signal ICLK, and outputs it as internal data IDQ (FIG. 1(e)). The internal data IDQ (D1) is thus transmitted to the internal circuit as lagging behind the external clock signal CLK by the delay time tD of the clock buffer. Subsequently, the write data D1 is amplified by a write amplifier and written to memory cells by sense amplifiers via an internal data bus.
When the memory cells for the read data Q1 to be read from and the memory cells for the write data D1 to be written to are the same, the output of the read data Q1 might be delayed if the write data D1 is written to the memory cells before the written data is read from the memory cells. To avoid access delay, SDRAMs of this type have an address comparator. Then, the address comparator compares the read address and the write address, and outputs the write data D1 as the read data Q1 directly if the two addresses are the same.
Here, in order to output the read data Q1 with the latency xe2x80x9c2xe2x80x9d, the comparison of the addresses and the selection of the read data in accordance with the comparison result must be completed between when the internal data IDQ (D1) is output and when the data output circuit starts to operate. More specifically, the comparison of the addresses and the selection of the read data must be completed within a margin time tMRG which elapses from the rising edge of the first internal clock signal ICLK to the rising edge of the second external clock signal CLK (adjusted clock signal DLLCLK).
Recent SDRAMs require operating frequencies of up to 250 MHz (clock cycle tCK=4 ns). For example, given that the clock cycle tCK is 4 ns and the operating delay of the clock buffer is 2 ns, the margin time tMRG must be less than or equal to 2 ns. If the margin time tMRG exceeds 2 ns, the clock cycle tCK needs to be extended in accordance with the margin time tMRG. That is, the maximum clock frequency can be restricted by the margin time tMRG.
The foregoing problem is not limited to the case shown in FIG. 1 where the read command R1 and the write command W1 are input successively. In general, the problem is common to situations where read data Q1 is output in synchronization with the clock next to the one at which write data D1 is received.
It is an object of the present invention to secure an operating margin for the internal circuit of a semiconductor memory device in order to increase a frequency of a clock signal.
According to one of the aspects of the semiconductor memory device of the present invention, a phase adjustment circuit delays an external clock signal by a predetermined amount to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal to adjust a delay time of the phase adjustment circuit in accordance with the comparison result. A data output circuit outputs read data from the memory cell array to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data written to the memory cell array in synchronization with the adjusted clock signal, the write data also being supplied to the data terminal. That is, the data output circuit and the data input circuit operate in synchronization with the same adjusted clock signal.
The cycle of the adjusted clock signal is the same as that of the external clock signal. Consequently, when the input of the write data and the output of the read data are performed in succession, the switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. In other words, the clock cycle can be reduced to the time required for the foregoing switching control. As a result, it is possible to prevent the maximum frequency of the external clock signal from being restricted by the time required for the switching control. The external clock signal can thus be increased in maximum frequency.
According to another aspect of the semiconductor memory device of the present invention, an address terminal receives a write address to select a memory cell to which data is written and a read address to select a memory cell from which data is read. An address comparator compares the write address and the read address received by the address terminal. A data selecting circuit outputs write data supplied in correspondence with the write address to the data output circuit, the write data outputted as read data corresponding to the read address, when result of the comparison by the address comparator indicates that the write address and the read address coincide with each other.
As stated above, the operation from the input of the write data to the output of the read data only has to be completed within one clock cycle. Consequently, the margin time necessary for the address comparison in the address comparator and for the data selection in the data selecting circuit can be extended to one clock cycle. When the clock cycle is restricted by the margin time, this restriction can be relaxed accordingly. That is, the maximum frequency of the external clock signal can be increased for an improved data transmission rate.
According to another aspect of the semiconductor memory device of the present invention, the phase adjustment circuit generates the adjusted clock signal which is in the same phase with the external clock signal. Consequently, the semiconductor memory device can receive the write data and output the read data completely in synchronization with the external clock signal. In other words, the system on which the semiconductor memory device is mounted only has to output the write data in synchronization with the external clock signal generated by the system itself, while surely receiving the read data in synchronization with the external clock signal.
According to another aspect of the semiconductor memory device of the present invention, the phase adjustment circuit generates the adjusted clock signal leading the external clock signal in phase. It is therefore possible to output the read data earlier than synchronizing the read data to the external clock signal, with a reduction in the access time in read operation.
According to another aspect of the semiconductor memory device of the present invention, a variable delay circuit adjusts a phase of the external clock signal or a phase of the adjusted clock signal to be compared by the phase comparator, in accordance with a command signal supplied to an external terminal. Thus, adjusting the phases of the clock signals in accordance with the electric characteristics of the semiconductor memory device allows characteristic defects to be relieved. This results in an enhanced fabrication yield.
According to another aspect of the semiconductor memory device of the present invention, a variable delay circuit adjusts a phase of the external clock signal or a phase of the adjusted clock signal to be compared by the phase comparator, in accordance with a command signal. A fuse circuit outputs the command signal for setting a delay time of the variable delay circuit. In accordance with the electric characteristics of the semiconductor memory device, the fuse circuit can be programmed to adjust the phases of the clock signals, thereby relieving characteristic defects. This results in an enhanced fabrication yield.